? semiconductor components industries, llc, 2009 august, 2009 ? rev. 3 1 publication order number: nb4l52/d nb4l52 2.5 v/3.3 v/5.0 v differential data/clock d flip-flop with reset multi ? level inputs to lvpecl translator w/ internal termination the nb4l52 is a differential data and clock d flip ? flop with a differential asynchronous reset. the differential inputs incorporate internal 50 termination resistors and will accept pecl, lvpecl, lvcmos, lvttl, cml, or lvds logic levels. when clock transitions from low to high, data will be transferred to the differential lvpecl outputs. the differential clock inputs allow the nb4l52 to also be used as a negative edge triggered device. the device is housed in a small 3x3 mm 16 pin qfn package. features ? maximum input clock frequency > 4 ghz typical ? 330 ps typical propagation delay ? 145 ps typical rise and fall times ? differential lvpecl outputs, 750 mv peak ? to ? peak, typical ? operating range: v cc = 2.375 v to 5.5 v with v ee = 0 v ? internal input termination resistors, 50 ? functionally compatible with existing 2.5 v/3.3 v/5.0 v lvel, lvep, ep, and sg devices ? ? 40 c to +85 c ambient operating temperature ? these are pb ? free devices marking diagram* http://onsemi.com qfn ? 16 mn suffix case 485g a = assembly location l = wafer lot y = year w = work week = pb ? free package *for additional marking information, refer to application note and8002/d. see detailed ordering and shipping information in the package dimensions section on p age 7 of this data sheet. ordering information 16 nb4l 52 alyw 1 data clock reset vtd vtclk d clk vtr r r d clk q hx x l ll zl lh zh z = low to high transition x = don?t care table 1. truth table figure 1. logic diagram d vtd clk vtclk vtr r q q (note: microdot may be in either location) 1
nb4l52 http://onsemi.com 2 r figure 2. pinout (top view) d d v td v td v cc q clk q v tclk v ee 1 2 3 4 5678 9 10 11 12 13 14 15 16 v tr r clk nb4l52 v tr exposed pad (ep) v tclk table 2. pin description pin name i/o description 1 v td ? internal 50 termination pin. (see table 4) 2 d ecl, cml, lvcmos, lvds, lvttl input noninverted differential input. (note 1) 3 d ecl, cml, lvcmos, lvds, lvttl input inverted differential input. (note 1) 4 v td ? internal 50 termination pin. (see table 4) 5 v tclk ? internal 50 termination pin. (see table 4) 6 clk ecl, cml, lvcmos, lvds, lvttl input noninverted differential input. (note 1) 7 clk ecl, cml, lvcmos, lvds, lvttl input inverted differential input. (note 1) 8 v tclk ? internal 50 termination pin. (see table 4) 9 v ee ? negative supply voltage 10 q ecl output inverted differential output. typically terminated with 50 resistor to v cc ? 2.0 v. 11 q ecl output noninverted differential output. typically terminated with 50 resistor to v cc ? 2.0 v. 12 v cc ? positive supply voltage 13 v tr ? internal 50 termination pin. (see table 4) 14 r lvecl, lvcmos, lvttl input noninverted differential reset input. (note 1) 15 r lvecl, lvcmos, lvttl input inverted differential reset input. (note 1) 16 v tr ? internal 50 termination pin. (see table 4) ? ep ? the exposed pad (ep) on the qfn ? 16 package bottom is thermally connected to the die for improved heat transfer out of package. the pad is not electrically connected to the die, but is recommended to be electrically and thermally connected to v ee on the pc board. 1. in the differential configuration when the input termination pin (vtd, vtd , vtr, vtr , vtclk, vtclk ) are connected to a common termination voltage or left open, and if no signal is applied on d/d ,clk/clk ,r/r input then the device will be susceptible to self ? oscillation.
nb4l52 http://onsemi.com 3 table 3. attributes characteristic value esd protection human body model machine model charged device model > 2 kv > 200 v > 1 kv moisture sensitivity (note 2) pb pkg pb ? free pkg qfn ? 16 level 1 level 1 flammability rating oxygen index: 28 to 34 ul 94 v ? 0 @ 0.125 in transistor count 164 meets or exceeds jedec spec eia/jesd78 ic latchup test 2. for additional information, see application note and8003/d. table 4. maximum ratings symbol parameter condition 1 condition 2 rating unit v cc positive power supply v ee = 0 v 6.0 v v ee negative power supply v cc = 0 v ? 6.0 v v io positive input/output negative input/output v ee = 0 v v cc = 0 v v i v cc v i v ee 6.0 ? 6.0 v v i in input current through r t (50 resistor) static surge 45 80 ma ma i out output current continuous surge 25 50 ma ma t a operating temperature range ? 40 to +85 c t stg storage temperature range ? 65 to +150 c ja thermal resistance (junction ? to ? ambient) 0 lfpm 500 lfpm 16 qfn 16 qfn 42 35 c/w c/w jc thermal resistance (junction ? to ? case) 2s2p (note 3) 16 qfn 4.0 c/w t sol wave solder pb ? free 265 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 3. jedec standard multilayer board ? 2s2p (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
nb4l52 http://onsemi.com 4 table 5. dc characteristics, clock inputs, lvpecl outputs (v cc = 2.375 v to 5.5 v, v ee = 0 v or v cc = 0 v, v ee = ? 2.375 to ? 5.5 v, t a = ? 40 c to +85 c) symbol characteristic min typ max unit i ee power supply current (inputs and outputs open) 16 25 ma v oh output high voltage (note 4, 5) v cc = 5.0 v v cc = 3.3 v v cc = 2.5 v v cc ? 1145 3855 2155 1355 v cc ? 1020 3980 2280 1480 v cc ? 895 4105 2405 1605 mv v ol output low voltage (note 4, 5) v cc = 5.0v v cc = 3.3v v cc = 2.5v v cc ? 1945 3055 1355 555 v cc ? 1770 3230 1530 730 v cc ? 1600 3400 1700 900 mv differential input driven single ? ended (figures 4 & 7) vth input threshold reference voltage range (note 6) 1050 v cc ? 150 mv v ih single ? ended input high voltage vth + 150 v cc mv v il single ? ended input low voltage v ee vth ? 150 mv differential input driven differentially (figures 5, 6 & 8 ) v ihd differential input high voltage 1200 v cc mv v ild differential input low voltage v ee v cc ? 150 mv v cmr input common mode range (differential configuration) (note 7) 1125 v cc ? 75 mv v id differential input voltage (v ihd ? v ild ) 150 v cc mv i ih input high current d / d , clk / clk , r /r (vtx/vtx open) ? 150 150 a i il input low current d / d , clk / clk , r /r (vtx/vtx open) ? 150 150 a r tin internal input termination resistor 40 50 60 note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. lvpecl outputs loaded with 50 to v cc ? 2.0 v for proper operation. 5. input and output parameters vary 1:1 with v cc . 6. v th is applied to the complementary input when operating in single ? ended mode. 7. v cmrmin varies 1:1 with v ee , v cmrmax varies 1:1 with v cc . the v cmr range is referenced to the most positive side of the differential input signal.
nb4l52 http://onsemi.com 5 table 6. ac characteristics v cc = 2.375 v to 5.5 v; v ee = 0 v or v cc = 0 v, v ee = ? 2.375 to ? 5.5 v (note 8) symbol characteristic ? 40 c 25 c 85 c unit min typ max min typ max min typ max v outpp output voltage amplitude (@ v inppmin ) (note 10) (see figure 4) f in 2.0 ghz f in 3.0 ghz f in 4.0 ghz 530 490 380 770 720 580 530 490 380 780 730 580 530 490 380 760 680 530 mv t plh , t phl propagation delay to clk to q, r to q output differential 300 400 500 300 400 500 300 400 500 ps t s setup time 100 100 100 ps t h hold time 50 50 50 ps t rr reset recovery 400 400 400 ps t pw minimum pulse width r/r 250 250 250 ps t jitter rms random clock jitter (note 9) f in 2.0 ghz f in 3.0 ghz f in 4.0 ghz 1 1 1 1 1 1 1 1 1 ps v inpp input voltage swing/sensitivity (differential configuration) (note 10) 150 2800 150 2800 150 2800 mv t r t f output rise/fall times @ 0.5 ghz (20% ? 80%) 80 135 190 80 145 190 80 155 190 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 8. measured by forcing v inpp (min) from a 50% duty cycle clock source. all loading with an external r l = 50 to v cc ? 2.0 v. input edge rates 40 ps (20% ? 80%). 9. additive rms jitter with 50% duty cycle clock signal. 10. input and output voltage swing is a single ? ended measurement operating in differential mode. f in , clock input frequency (ghz) figure 3. output voltage amplitude (v outpp ) vs. clock input frequency at ambient temperature (typical). v outpp , output voltage amplitude (mv) (typical) 700 600 500 400 300 200 100 0 4 1 02 800 3
nb4l52 http://onsemi.com 6 figure 4. differential input driven single ? ended clk/d/r figure 5. differential inputs driven differentially clk/d/r v th v th clk /d /r v ihd v ild v id = |v ihd ? v ild | clk/d/r figure 6. differential inputs driven differentially v ih v il clk /d /r clk /d /r v ihmax v ilmax v ihmin v ilmin v cc v thmax v thmin v ee v th v ihdmax v ildmax v ihdmin v ildmin v cmr v cc v cmmax v cmmin v ee figure 7. v th diagram figure 8. v cmr diagram clk clk clk/d/r q q t phl t plh v inpp = v ih ? v il v outpp = v oh (q) ? v ol (q) figure 9. ac reference measurement clk /d /r
nb4l52 http://onsemi.com 7 figure 10. typical termination for output driver and device evaluation (see application note and8020/d ? termination of ecl logic devices.) driver device receiver device qd q d z o = 50 z o = 50 50 50 v tt v tt = v cc ? 2.0 v nb6l239 ordering information device package shipping ? NB4L52MNG qfn ? 16, 3 x 3 mm (pb ? free) 123 units / rail nb4l52mnr2g qfn ? 16, 3 x 3 mm (pb ? free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. resource reference of application notes an1405/d ? ecl clock distribution techniques an1406/d ? designing with pecl (ecl at +5.0 v) an1503/d ? eclinps i/o spice modeling kit an1504/d ? metastability and the eclinps family an1568/d ? interfacing between lvds and ecl an1672/d ? the ecl translator guide and8001/d ? odd number counters design and8002/d ? marking and date codes and8020/d ? termination of ecl logic devices and8066/d ? interfacing with eclinps and8090/d ? ac characteristics of ecl devices
nb4l52 http://onsemi.com 8 package dimensions 16 pin qfn case 485g ? 01 issue d 16x seating plane l d e 0.15 c a a1 e d2 e2 b 1 4 58 12 9 16 13 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. 5. l max condition can not violate 0.2 mm minimum spacing between lead tip and flag ??? ??? ??? b a 0.15 c top view side view bottom view pin 1 location 0.10 c 0.08 c (a3) c 16 x e 16x note 5 0.10 c 0.05 c a b note 3 k 16x dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.18 0.30 d 3.00 bsc d2 1.65 1.85 e 3.00 bsc e2 1.65 1.85 e 0.50 bsc k l 0.30 0.50 exposed pad 0.18 typ l1 detail a l alternate terminal constructions ?? ?? 0.00 0.15 mm inches scale 10:1 0.50 0.02 0.575 0.022 1.50 0.059 3.25 0.128 0.30 0.012 3.25 0.128 0.30 0.012 exposed pad *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 nb4l52/d the products described herein (nb4l52), may be covered by u.s. patents including 6,362,644 . there may be other patents pending. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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